1. Field of the Invention
The present invention relates to a high speed semiconductor type memory device. More particularly, the present invention relates to a semiconductor type memory device such as a synchronous DRAM, performing high-speed and consecutive access in a column direction.
2. Description of the Related Art
FIG. 8 shows the structure of a conventional synchronous DRAM. The synchronous DRAM shown in FIG. 8 has a burst mode capable of consecutively accessing memory cells corresponding to addresses from a specified start address to the specified start address +1, the specified start address +2, the specified start address +4, or the specified start address +8.
In FIG. 8, a command decoder 11 receives a /RAS signal, a /CAS signal, a /CS signal, and a /WE signal. The command decoder 11 decodes these signals so as to generate an instruction for causing a bank to be selected to be in an active state, a read state, or a write state, an instruction for activating a mode register 112, and the like. In accordance with a standard specification for a 16M bit synchronous DRAM, the instruction for activating the mode register 112 is generated when all of the /RAS signal, the /CAS signal, the /CS signal and the /WE signal are at an "L" level. In response to the instruction for activating the mode register 112, the synchronous DRAM of FIG. 8 enters a mode register set mode.
In the mode register set mode, when the mode register 112 receives an address, the mode resister 112 decodes the address so as to generate a burst length signal, a burst type, and a CAS latency.
The "burst length signal" refers to the number of a series of data which are consecutively accessed (e.g., the number of series of addresses). In accordance with the standard specification for the 16M bit synchronous DRAM, 1, 2, 4, or 8 (in the case of a sequential type), a full page is added as a burst length is set. The "burst type" refers to a sequence of addresses which are consecutively accessed, and the burst type includes the sequential type and an interleaved type. The "CAS latency" refers to the number of clocks from the time of a column address input to the time of a data input and output. In accordance with the standard specification for the 16M bit synchronous DRAM, 1, 2, or 3 is set as the CAS latency.
When the synchronous DRAM of FIG. 8 enters the mode register set mode, a burst operation is performed as follows.
When a start address is input to a counting unit 13, the counting unit 13 sequentially increments a column address, starting from the start address. The series of column addresses are sequentially output to a memory array 14. The memory array 14 accesses memory cells corresponding to the series of column addresses.
A setting unit 115 receives the start address and the burst length signal from the mode register 112. The setting unit 115 generates an ending address based on the start address and the burst length signal.
A stopping unit 16 receives the column address from the counting unit 13 and the ending address from the setting unit 115. When the column address reaches the ending address, the stopping unit 16 outputs a counter stop signal to the counting unit 13. In response to the counter stop signal, the counting unit 13 stops outputting the column address to the memory array 14.
As a result, in the memory array 14, memory cells corresponding to one row address and addresses from the start address to the ending address are accessed.
Each of FIGS. 9, 10, and 11 shows a relationship between a burst length signal BL in the synchronous DRAM of FIG. 8 and accessed data.
When 8 is set as the burst length signal BL, eight addresses from the start address are accessed and eight data are output. Then, the stopping unit 16 outputs the counter stop signal to the counting unit 13. The counting unit 13 thereby stops outputting an address to the memory array 14. If a burst stop instruction is input during the burst operation, the burst operation is suspended. Upon reading out data, an I/O terminal (not shown) of the synchronous DRAM of FIG. 8 is switched to be a high impedance after the CAS latency passed from the input of the burst stop instruction. Upon writing data, simultaneously with the input of the burst stop instruction, the I/O terminal (not shown) is switched to be a high impedance.
According to the synchronous DRAM of FIG. 8, 1, 2, 4, and 8 are preset as the burst length signal BL and any of these settings is selected.
For example, in the case where nine addresses from a start address are accessed, 9 cannot be set as the burst length signal BL. Therefore, the nine addresses from the start address are accessed in the manner shown in a timing chart of FIG. 10.
First, 8 is selected as the burst length signal BL. Then, eight addresses from a start address are accessed. Next, 1 is selected as the burst length signal BL, and one address from a start address is accessed.
As described above, in the case where selection of the burst length signal BL is performed more than once, additional time is required in order to complete access of all the desired addresses. Also in the case where eighteen or twenty addresses from the start address, for example, are accessed, the same problem arises.
For example, when a full page is set as the burst length signal BL (e.g., 256 is set as the burst length signal BL) and nine addresses from a start address are accessed, the burst stop instruction is input so as to stop the access as shown in FIG. 11. Accessing nine addresses from the start address implies difficulty in timing control due to dependency on the input timing of the burst stop instruction.